? semiconductor components industries, llc, 2001 january, 2001 rev. 3 1 publication order number: mc100lvel29/d mc100lvel29 3.3vecl dual differential data and clock d flip-flop with set and reset the mc100lvel29 is a dual masterslave flip flop. the device features fully differential data and clock inputs as well as outputs. the mc100lvel29 is pin and functionally equivalent to the mc100el29. data enters the master latch when the clock is low and transfers to the slave upon a positive transition on the clock input. the differential inputs have special circuitry which ensures device stability under open input conditions. when both differential inputs are left open the d input will pull down to v ee and the d input will bias around v cc /2. the outputs will go to a defined state, however the state will be random based on how the flip flop powers up. both flip flops feature asynchronous, overriding set and reset inputs. note that the set and reset inputs cannot both be high simultaneously. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? 1100 mhz flipflop toggle frequency ? esd protection: >2 kv hbm ? 580 ps typical propagation delays ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 3.8 v ? internal input pulldown resistors ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 313 devices http://onsemi.com marking diagram* 1 20 a = assembly location wl = wafer lot yy = year ww = work week soic20 dw suffix case 751d 100lvel29 awlyyww 1 20 device package shipping ordering information mc100lvel29dw soic20 38 units/rail mc100lvel29dwr2 soic20 1000 units/reel *for additional information, see application note and8002/d
mc100lvel29 http://onsemi.com 2 v bb logic diagram and pinout: 20-lead soic (top view) clk0 d1 clk1 17 18 16 15 14 13 12 4 3 5678 9 q0 11 10 q0 s0 s1 v cc q1 q1 v ee d0 19 20 2 1 r0 v cc clk0 d1 d0 clk1 r1 clk d s r q q clk d r s q q r l l h l h truth table s l l l h h d l h x x x clk z z x x x q l h l h undef z = low to high transition x = don't care q h l h l undef pin description function ecl differential data inputs ecl reset inputs ecl differential clock inputs ecl differential clock inputs ecl set inputs ecl differential data outputs reference voltage output positive supply negative supply pin d0, d0 ; d1, d1 r0, r1 clk0, clk0 clk1, clk1 s0, s1 q0, q0 ; q1, q1 v bb v cc v ee warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. maximum ratings (note 1.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v 8 to 0 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6o0 6 to 0 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 20 soic 20 soic 90 60 c/w c/w q jc thermal resistance (junction to case) std bd 20 soic 30 to 35 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur.
mc100lvel29 http://onsemi.com 3 lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 35 50 35 50 35 50 ma v oh output high voltage (note 2.) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2.) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ended) 1490 1825 1490 1825 1490 1825 mv v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential) (note 3.) vpp < 500 mv vpp 500 mv 1.3 1.5 2.9 2.9 1.2 1.4 2.9 2.9 1.2 1.4 2.9 2.9 v v i ih input high current 150 150 150 m a i il input low current dn dn 0.5 300 0.5 300 0.5 300 m a m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1 v. lvnecl dc characteristics v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 35 50 35 50 35 50 ma v oh output high voltage (note 2.) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 2.) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (single ended) 1165 880 1165 880 1165 880 mv v il input low voltage (single ended) 1810 1475 1810 1475 1810 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3.) vpp < 500 mv vpp 500 mv 2.0 1.8 0.4 0.4 2.1 1.9 0.4 0.4 2.1 1.9 0.4 0.4 v v i ih input high current 150 150 150 m a i il input low current dn dn 0.5 300 0.5 300 0.5 300 m a m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between v pp min and 1 v.
mc100lvel29 http://onsemi.com 4 ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 3.3 v (note 1.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 1.1 1.1 1.1 ghz t plh t phl propagation delay clk to output s, r 480 480 680 700 500 500 580 700 720 520 520 720 740 ps t s t h setup time hold time 0 100 0 100 0 100 ps t rr set/reset recovery 100 100 100 ps t pw minimum pulse width clk, set, reset 400 400 400 ps t jitter cycletocycle jitter tbd tbd tbd ps v pp input swing (note 2.) 150 1000 150 1000 150 1000 mv t r t f output rise/fall times q (20% 80%) 280 550 280 550 280 550 ps 1. v ee can vary 0.3 v. 2. v pp (min) is the minimum input swing for which ac parameters guaranteed. v tt = v cc 2.0 v figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lvel29 http://onsemi.com 5 package dimensions soic20 dw suffix plastic soic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc100lvel29 http://onsemi.com 6 notes
mc100lvel29 http://onsemi.com 7 notes
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